Introduction
| IP Core | IP Core Category |
|---|---|
| Nios V/g Processor Intel FPGA IP | Processors and Peripherals |
| IOPLL Intel FPGA IP | PLL |
| Reset Release Intel FPGA IP | Configuration and Programming |
| JTAG to Avalon Master Bridge Intel FPGA IP | Memory Mapped |
Detailed Description
The design demonstrates synchronous control of up to two three-phase permanent magnet synchronous motors (PMSMs) or brushless DC (BLDC) motors. You can adapt the design to other motor types. For simplicity, the Drive-On-Chip for Intel Agilex® 7 Devices is published with a power board and motor model synthetized and programmed in the same FPGA fabric removing the need for a physical motor setup. The motor and power board model were designed using Intel’s DSP Builder Advanced Blockset. The resulting model is included in this example design package. The user needs only an Agilex® 7 FPGA Development Kit to run the example, the motor and power model helps to tune and test the control system before using a physical power stage. The motor and power board model are based on the former Intel® Tandem Motion 48V board, described in AN773 and AN669.